1. Technical Field
The present invention relates generally to a semiconductor circuit, and more particularly to a phase correction circuit.
2. Related Art
A semiconductor circuit, for example, a dynamic random access memory (DRAM), uses a clock signal as a reference signal for a read or write operation.
Specifically, the standard for graphic DRAMs, for example, GDDR5 DDR SDRAMs, specifies use of multi-phase signals (e.g., 4-phase clock signals).
The 4-phase clock signals may be generated by separating the phases of 2-phase clock signal provided externally.
In a graphic DRAM, a phase separator separates the phases of a 2-phase clock signal received through a receiver and generates 4-phase clock signals.
When the duty ratio of an externally provided 2-phase clock signal is exactly 50:50, any two of the 4-phase clock signals generated by separating the phases of the 2-phase clock signal would have the phase difference of exact 90° therebetween.
However, when there is a skew in the duty ratio of the 2-phase clock signal, a phase skew will occur in the 4-phase clock signals ICLK, QCLK, ICLKB, QCLKB as illustrated in FIG. 1 although the duty of each of the 4-phase clock signals is maintained constant.
That is, among the 4-phase clock signals ICLK, QCLK, ICLKB, QCLKB, the phases of ICLK and ICLKB are opposite to each other or have a phase difference of 180° therebetween, and the phases of QCLK and QCLKB also have a phase difference of 180° therebetween. However, the signals ICLK and QCLK do not have a phase difference of 90° therebetween.
As described above, when a phase skew occurs in the 4-phase clock signals, the set up margin or hold margin of a circuit that receives or transmits data using the 4-phase clock signals may be reduced.